//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// External Clocked RAM Cell for M8051W/EW External Data Memory
// 
// $Log: cxram.v,v $
// Revision 1.6  2002/01/09
// Final testbench changes for version2
//
// Revision 1.5  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/11/14
// First EW checkin
//
// Revision 1.4  2000/03/06
// Revised configuration scheme
//
// Revision 1.3  2000/02/05
// Name change from m8051e to m8051ewarp
//
// Revision 1.2  1999/11/19
// SFR read enable modelling added, corrections to debug testing.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      :       Configurable RTL clocked RAM cell for modelling External
//              :       RAM for use with the M8051W/EW Soft Core
//
////////////////////////////////////////////////////////////////////////////////

`suppress_faults
`include "m8051w_tb_cfg.v"

module cxram(DO, A, DI, RNW, NCS, NOE, CLK);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //

parameter PreLoad = 0;                            // Load data from file

output	[7:0]	DO;
input	[(`XramALines - 1):0]	A;
input	[7:0]	DI;
input 		RNW, NCS, NOE;
input           CLK;

reg	[7:0]	MEM [0:(`XramSize - 1)];
reg     [7:0]	read_data;

integer i;

// Put all memory locations into a pre-determined state at simulator start time
// and optionally load the program image from file.

initial
begin
  for (i = 0; i < `XramSize; i = i +1)
    MEM[i] = `Uninitialised;
  if (PreLoad) $readmemh("program.rom", MEM);
end

// Register write transfers
always @(posedge CLK)
  if (~NCS && ~RNW)
    if (^A === 1'bx) begin
      $display("Bus Error:   At time %t, XRAM address indeterminate during write: %b",
               $time, A);
      for (i = 0; i < `XramSize; i = i +1) MEM[i] = 8'hxx;
      end
    else
      MEM[A] <= DI;

// Model clocked array access
always @(posedge CLK)
  if (~NCS && RNW)
    if (^A === 1'bx) begin
      //$display("Bus Error:   At time %t, XRAM address indeterminate during read : %b",
      //         $time, A);
      read_data <= #(`Thclk * 0.2) `BadData;
      end
    else begin
      read_data <= #(`Thclk * 0.2) `BadData;
      read_data <= #`Txramacc MEM[A];
      end

assign DO = NOE !== 1? read_data: 8'hzz;

endmodule

`nosuppress_faults
